Question on SR latch functionality

Question

Below is the diagram of SR latch

The following is the functional table as per my scrutiny .

Sl.no    S | R    Q(t) | Q'(t)    Q(t+1) | Q'(t+1)    Q(t+2) | Q'(t+2)   Q(t+3) | Q'(t+3)   Remark
=====   ===|===  ======|======    =======|=======    ========|========  ========|========= ========
1        0 | 0       0 | 0             1 | 1               0 | 0              1 | 1        Oscillaton
2        0 | 0       0 | 1             0 | 1               0 | 1              0 | 1        Stable(Hold)
3        0 | 0       1 | 0             1 | 0               1 | 0              1 | 0        Stable(Hold)
4        0 | 0       1 | 1             0 | 0               1 | 1              0 | 0        Oscillaton
5        0 | 1       0 | 0             0 | 1               0 | 1              0 | 1        Stable
6        0 | 1       0 | 1             0 | 1               0 | 1              0 | 1        Stable(Reset)
7        0 | 1       1 | 0             0 | 0               0 | 1              0 | 1        Stable-1(Reset)
8        0 | 1       1 | 1             0 | 0               0 | 1              0 | 1        Stable-1
9        1 | 0       0 | 0             1 | 0               1 | 0              1 | 0        Stable
10       1 | 0       0 | 1             0 | 0               1 | 0              1 | 0        Stable-1(Set)
11       1 | 0       1 | 0             1 | 0               1 | 0              1 | 0        Stable(Set)
12       1 | 0       1 | 1             0 | 0               1 | 0              1 | 0        Stable-1
13       1 | 1       0 | 0             0 | 0               0 | 0              0 | 0        Stable
14       1 | 1       0 | 1             0 | 0               0 | 0              0 | 0        Stable
15       1 | 1       1 | 0             0 | 0               0 | 0              0 | 0        Stable
16       1 | 1       1 | 1             0 | 0               0 | 0              0 | 0        Stable

Notation :

Stable : Stable output state

Stable-1 : Stable output state after one time unit delay

Set , Reset , Hold are as per normal usage.

My doubts :

1) If S=R=1 , output is stable and is 0,0 . Is this state undesirable or undefined or invalid ?

2) Why Q and Q' must always be complement to each other ? Is it necessary for the reason "to prevent oscillations in 1,4" ?

3) Suppose if we assume that we prevent S=R=1 and Q=Q' . But then in 7,10 why stable state(Set/Reset) not took place in next state itself ? Is this type of delay accepted ?

@Raphael 1)But all the 3 doubts i asked are related to one another . 2)And there is another question on SR latch http://cs.stackexchange.com/questions/10614/how-to-understand-the-sr-latch . Is it also off-topic here ? — hanugm, Sep 09 '14 at 10:22
@hanu, questions about digital design are on-topic here. They are also on-topic at Electrical Engineering. You would probably get an answer at Electrical Engineering more quickly. — Wandering Logic, Sep 09 '14 at 11:23
But I am wondering why some one down-voted my question , which is not of type "Low standard" or "Do my home work" type . Is there any way to report these fake down-votes ? — hanugm, Sep 09 '14 at 11:26
Down votes are part of stack exchange. It is how other users encourage you to improve your question (or answer). In the case of this question someone (quite legitimately) felt that the question could be improved. For instance, @Raphael pointed out that your question title is way too generic and that you appear to ask three different questions (it may be the case that your questions are really three aspects of the same thing, but it is your responsibility to make that clear.) — Wandering Logic, Sep 09 '14 at 12:07

score 2 · Answer 1 · answered Sep 09 '14 at 12:02

In digital design we are approximating a digital function with a continuous function. The SR latch is one of the (many) cases where the abstraction only holds over some but not all of the possible continuous conditions.

In the case of the SR latch you need to remember that the two input signals do not transition at exactly the same time. Nor do they switch instantaneously from 0 to 1. All your questions are indeed related. The illusion of an SR latch breaks down if you look at the outputs too quickly after the inputs change, or cause the continuous (analog) circuit to oscillate, or ever get into a condition where the inputs are stable at a value close to 1/2, or get into a condition where the inputs are significantly less than 0 or greater than 1.

The 0,0 state is undesirable for several reasons. The circuit that comes next may be relying on the invariant that Q' = not(Q). And, as you pointed out, it can lead to oscilations.

The S=R=1 input leads to a stable 0,0 output, but what happens next? If you bring S and R back down to 0 "simultaneously" any of three things could happen: (1) S could go to 0 slightly more quickly than R goes to 0, in which case it's like you did S=0, R=1, and the output will become 0,1. (2) S could go to 0 slightly slower than R goes to 0, in which case it's like you did S=1, R=0 and the output will become 1,0. (3) S and R could go to 0 sufficiently close together to make the circuit oscilate.

As to your third question about the "next state", your assumption that you are going through discrete states is not correct. You are transitioning from one state that has a stable digital interpretation to another state that has a stable digital interpretation. It takes some time for this transition to occur, and that is part of the specification of the circuit: you can't "look" at the output of the circuit too soon after the inputs change.

Question on SR latch functionality

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