The present state Q2,Q1,Q0 of the counter before applying the clock pulse was (101). If the input Clock frequency to the circuit is 100KHz, then the output frequency of the circuit will be ?
My Approach: I have built the state table and I concluded that from 101 it goes to 010 and from 010 to 101 again so it acts like mod-2 counter. But I don't understand the part in which we're applying frequency. Can someone help me to visualize it?
The J-K Flip-Flops in your circuit are positive edge triggered, (since they have a > mark on the clock input of their schematic.)
Positive edge triggered means that the Flip-Flops are triggered on the rising edge of the clock.
If the input frequency is $f$, the time between 2 successive rising edges of the input clock is $1/f$ seconds.
The output toggles on the rising edge of the input clock, since the output goes from 101 -> 010 -> 101 and so on. So each bit of the output becomes HIGH on a rising edge of the clock and LOW on the subsequent rising edge of the clock. In other words, each bit of the output becomes HIGH on every second rising edge of the input clock. Thus, each bit of the output becomes HIGH every $2 / f$ seconds. The frequency of the output is then $f / 2$ Hz.
For f = 100 kHz, the output is f = $(100 * 10^3 / 2)$ Hz = 50 kHz
Computer simulation results:
In the waveform above, which is created from a simulation of your circuit, clk is the input clock and q is the output. q[2], q[1], and q[0] represent the outputs of the Q2, Q1 and Q0 flip-flops respectively.
From the waveform it can be observed that frequency of the output is half of that of the input.