Why S=1, R=1 Is forbidden in RS-Flip Flop

Question

I have come across about RS Flip Flop & I have tried implementing that on a simulator & using actual logic gates. But I'm still not sure whether I have correctly understood the case unstable or the forbidden case S=1, R=1 in Flip flop. Can anyone tell me what exactly is that?

By the way I have used 2-INPUT NAND Gates to implement the flip Flop. What is the difference between the NAND Gate Flip Flop & NOR Gate Flip Flop, ?

Hello and Welcome, your question fits better in [electronics.SE] please ask there, and you'll get better answers. Thanks! (MODS - flag to migrate?) — Ran G., Mar 27 '13 at 00:35
Also, check the already-answered SR-FF questions they have there, like this one and that one. — Ran G., Mar 27 '13 at 00:45
@Gilles, yes, I believe so.. We need to draw a line, and this, IMHO, is a clear hardware, EE, signal-level issue. Let's continue in meta. — Ran G., Mar 27 '13 at 01:37
Besides the question whether this is ontopic, the question can be improved in terms of clarity in presentation, both in terms of language and what the actual question is. — Raphael, Mar 27 '13 at 12:01
This question has been cross-posted and answered on EE.SE: http://electronics.stackexchange.com/questions/62501/why-is-s-1-r-1-state-forbidden-in-rs-flip-flop and the first question Gilles mentioned is on CS.SE, too: http://cs.stackexchange.com/questions/10614/how-to-understand-the-sr-latch. This makes this one here a duplicate. — frafl, Apr 04 '13 at 19:38
@frafl Since we can't mark questions as duplicates across sites, I added a reference to the answer as CW so we can have this question dealt with appropriately. — Raphael, Apr 05 '13 at 10:16
@RanG. I'm closing it, not because I think it's off-topic (I don't, and the meta discussion tends towards its being on-topic), but as a multipost that has been answered on another site. — Gilles 'SO- stop being evil', Apr 07 '13 at 15:18

score 0 · Answer 1 · edited Apr 13 '17 at 12:33

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This question has an accepted answer on another site.

Digest: If you had both inputs set to $1$, both outputs would be $0$ but they are supposed to be complementary.

edited Apr 13 '17 at 12:33

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answered Apr 05 '13 at 10:15

Raphael

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Why S=1, R=1 Is forbidden in RS-Flip Flop

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